This invention relates to the field of semiconductor memories, and more particularly to a method and manufacture for decreasing charge leakage in a non-volatile semiconductor memory.
The demand for inexpensive, easily accessible and compact long term information storage systems continues to increase. In the past, the demand for long term information storage was met by archiving paper records. Today, however, the volume of information requiring storage makes this solution impractical. Recently, the demand for long term information storage has been met by magnetic media information storage systems and optical information storage systems. Although these systems have excellent long term information retention capability, in some applications they are not sufficiently compact. So, a current trend is to use non-volatile semiconductor memory for long term information storage.
Non-volatile semiconductor memory is compact and permits rapid access to the stored information. Information is stored in a non-volatile semiconductor memory as electronic charge. The magnitude of the electronic charge is used to represent a binary value. For instance, in some memory systems the presence of charge represents a binary one, and the absence of charge represents a binary zero. In other memory systems, a larger charge magnitude represents a binary one, and a smaller charge magnitude represents a binary zero. In either system, charge isolation is critical to successful long term information storage.
Charge isolation implies that once an electronic charge is located in a structure, the charge remains at that location indefinitely. In the art, charge is located in a structure such as a transistor having a control gate, a floating gate, a drain, a source, and a dielectric composite insulator interposed between the control gate and the floating gate. In operation, the control gate induces an electronic charge to locate at the floating gate. Once the charge is induced at the floating gate, for the transistor device to successfully operate as a long term information storage device, the charge must remain at the floating gate for a long period of time. As devices are scaled to create higher density memory, the thickness of the dielectric is reduced to maintain the same coupling. As the thickness is reduced, the ability to prevent electron migration through the insulator becomes difficult. The rate of this charge leakage defines the time that a non-volatile semiconductor memory can function as a long term information storage device.
To successfully substitute for magnetic or optical storage devices as a long term information storage device, a non-volatile semiconductor memory device, such as an EPROM, EEPROM, or a flash EPROM, must store information reliably for at least ten years, so any charge leakage from the floating gate is detrimental to the use of non-volatile semiconductor memory as a long term information storage device.
For these and other reasons there is a need for the present invention.
The above mentioned problems with charge leakage in memory cells and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A method and composite for decreasing charge leakage is described.
The dielectric composite insulator of the present invention, by reducing the charge leakage from the floating gate to the control gate of a memory cell, provides for an improved non-volatile semiconductor memory cell. Reducing the charge leakage in a non-volatile semiconductor memory makes the memory a more viable long term information storage device.
A non-volatile semiconductor memory cell includes a semiconductor substrate, a source and drain formed on the semiconductor substrate, an insulator formed on the source and drain, a floating gate formed on the insulator, a composite formed on the floating gate and a control gate formed on the composite.
In one embodiment of the present invention, a layer of undoped polysilicon, amorphous silicon, or amorphous polysilicon is located between the floating gate and the layer of silicon dioxide. In an alternate embodiment of the present invention, a layer of silicon rich nitride is deposited on the layer of silicon nitride and then oxidized to form the silicon dioxide layer. In still another embodiment of the present invention, a layer of undoped polysilicon, amorphous silicon, or amorphous polysilicon is located between the floating gate and the silicon dioxide, and a layer of silicon rich nitride is located between the layer of silicon nitride and the silicon dioxide of the composite. The effect of interposing a layer of undoped polysilicon, amorphous silicon, or amorphous polysilicon, which in some designs is thin, or a layer of silicon rich nitride, which in some designs is thin, or both into the composite is to decrease the charge leakage from the floating gate to the control gate of the memory cell. A thin layer of undoped polysilicon, amorphous silicon, or amorphous polysilicon is a layer having a thickness of less than about one-hundred angstroms, and a thin layer of silicon rich nitride is a layer having a thickness of less than about one-hundred angstroms.
Another embodiment of the present invention also includes a process for forming the dielectric insulating composite. In the art, the process for forming the composite comprises depositing a layer of silicon dioxide on the floating gate, depositing a layer of silicon nitride on the layer of silicon dioxide, and depositing a layer of silicon dioxide on the layer of silicon nitride. In the present invention, the process for forming the dielectric insulating composite comprises, in addition to the steps of the process for forming the composite, the steps of either depositing a layer of undoped polysilicon, amorphous silicon, or amorphous polysilicon or depositing a layer of silicon rich nitride, or both. In addition, in one embodiment of the process, after forming the floating gate by flowing silane and phosphine, the deposition of the layer of undoped polysilicon, amorphous silicon, or amorphous polysilicon is accomplished by reducing the flow of phosphine. In an alternate embodiment of the process, after depositing a layer of silicon nitride formed on the layer of silicon dioxide by flowing dichlorosilane and ammonia, the deposition of the silicon rich nitride layer is accomplished by reducing the flow of ammonia. And in still another embodiment, after depositing the layer of silicon nitride formed on the layer of silicon dioxide by flowing tetrachlorosilane and ammonia, the deposition of the silicon rich nitride layer is accomplished by reducing the flow of ammonia.